1. Field of the Invention
This invention relates to the characterization of ASIC performance margin relative to frequency, and particularly to the characterization of that margin without the use of hardware external to the ASIC in order to stimulate the ASIC in order to characterize that margin, and characterization of all parts produced rather than a subset.
2. Description of Background
The characterization of the hardware behavior relative to performance margin (or timing margin) is an expensive measurement in terms of capital equipment, staff, and time, and performed on a small number of parts in the life of a program. The issue is how to best characterize the margin of a timing test which is performed inside an ASIC, but normally the test is performed on a clock and data arriving from inputs external to the ASIC. As an example, the system is a synchronous memory interface ASIC chip therein after referred to as “SMI ASIC”) connected to one or more SDRAM devices. The capture of read data from SDRAM to SMI is a critical timing test. Prior to release of the SMI to be built, this test is timed using some timing method, such as static timing or SPICE Model. These timing tools model timing effects due to process, voltage, and temperature variation. In a typical case, the correlation of the timing model to hardware is imperfect, and the degree of variation is unknown. In order to release the chip to foundry with low risk of failing timing, the models are pessimistic. But over-pessimistic timing models increase the engineering effort required to release, and delay time-to-market. Other factors involved are the process spread of the SMI, the fact that multiple SDRAM speed grades are available so the SMI must operate over a range of frequency, and binning or sorting of the part may be required. In order to verify that the test is met across the supported process, temperature, and voltage range at all frequencies, characterization of the part after manufacturing is required. This characterization is expensive (staff, equipment, and time), and the quality of the characterization is usually suspect even if significant expense is allocated to the task because the number of parts characterized is limited. It is difficult to characterize only the chip degradation relative to the timing test; regardless of the method of injecting inputs externally, the external injector injects some amount of degradation, which can be considered system degradation, which must be removed from the chip characterization results. It would be desirable to remove the system degradation from the chip characterization.